FIFO buffer to cache memory

Details FIFO buffer to cache memory FIFO buffer to cache memory

1982-05-12

1985-01-15

Smith, Jerry

Boots, shoes, and leggings

G06F 1300

Patent

active

044941900

ABSTRACT:
A minicomputer system is disclosed having a megabus with a plurality of processors and/or subprocessors, input/output (I/O) units and including logic for enabling the detection, decoding, storage and dispatching of data and instructions between the megabus and associated processors. The logic detects information addressed to its associated processors and synchronizes the transfers between the independently timed asynchronous processors and the units attached to the megabus.

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