MOS/SOS Process

Details MOS/SOS Process MOS/SOS Process

1979-04-20

1981-06-16

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29578, 29579, 148 15, 148187, 357 42, H01L 2122

Patent

active

042728800

ABSTRACT:
An MOS process for fabricating multi-layer integrated circuits particularly suited for SOS fabrication is disclosed. Transistors are fabricated both on the substrate level and in an overlying polysilicon layer. Processing techniques for aligning source and drain regions with a buried gate are described. In one embodiment, a photoresist layer is exposed to light directed through the sapphire substrate, thereby employing the buried gate as a masking member. Laser annealing may be used to provide larger crystals of silicon in the polysilicon layer.

REFERENCES:
patent: 3585088 (1971-06-01), Schwuttke et al.
patent: 3639813 (1972-02-01), Kamoshida et al.
patent: 4033026 (1977-07-01), Pashley
patent: 4174217 (1979-11-01), Flatley

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