Microprocessor controlled phase locked loops

Details Microprocessor controlled phase locked loops Microprocessor controlled phase locked loops

1981-12-09

1985-01-15

LaRoche, Eugene R.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 1R, 331 2, 331 14, 331 18, 307510, 328 14, H03K 700, H03K 526

Patent

active

044940793

ABSTRACT:
A digital counter is phased locked to a reference frequency by a voltage trolled oscillator which causes the counter to increase its count rate or decrease its count rate in accordance to the presence of a one or a zero on the most significant bit of the counter at the halfway point of one cycle of the reference frequency. The counter is reset at the end of the cycle of the reference frequency. A single microprocessor which can assess this most significant bit (MSB) and vary the oscillator output, can in this manner control any number of independent phase lock loop circuits.

REFERENCES:
patent: 3806825 (1974-04-01), Schlosser
patent: 4219784 (1980-08-01), Detering
patent: 4301423 (1981-11-01), Mulder
patent: 4305045 (1981-12-01), Metz et al.
patent: 4380742 (1983-04-01), Hart
patent: 4450518 (1984-05-01), Klee
patent: 4453136 (1984-06-01), Kelland

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