Metal working – Method of mechanical manufacture – Assembling or joining
Patent
1979-10-19
1981-05-19
Ozaki, G.
Metal working
Method of mechanical manufacture
Assembling or joining
148 15, 148187, 357 23, 357 91, H01L 2128
Patent
active
042676320
ABSTRACT:
A process for fabricating an MOS electrically programmable memory array which includes a plurality of floating gate memory devices is disclosed. The process employs two layers of polysilicon, each of which are used to define a plurality of spaced-apart parallel lines with the lines of the other layer. Doped bit line regions are formed in the substrate in alignment with the first lines prior to the fabrication of the second lines. The first lines are etched in alignment with the second lines to define floating gates. Overlying metal lines (bit lines) are formed over the doped regions and coupled to the doped regions through periodic contacts. Substantially fewer contacts are required than in prior art arrays, permitting the fabrication of a higher density array.
REFERENCES:
patent: 3996657 (1976-12-01), Simko et al.
patent: 4033026 (1977-07-01), Pashley
patent: 4095251 (1978-06-01), Dennard et al.
patent: 4114255 (1978-09-01), Salsbury et al.
patent: 4142926 (1979-03-01), Morgan
patent: 4151021 (1979-04-01), McElroy
patent: 4178674 (1979-12-01), Liu et al.
Intel Corporation
Ozaki G.
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