Excavating
Patent
1982-03-26
1984-05-22
Atkinson, Charles E.
Excavating
371 49, G06F 1110
Patent
active
044505620
ABSTRACT:
A memory system comprised of M integrated circuits (IC's) in which M-1 of the IC's store data bits and the Mth IC stores system parity bits. Each IC includes a memory array of cells organized into W internal words of several bits, a parity array for storing a parity bit for each internal word, means for reading-out a selected bit, means for reading the internal word containing the selected bit and ascertaining whether its parity is correct and for producing a first signal indicative thereof. Each IC also includes means responsive to its selected data bit and to an externally generated signal indicative of the parity of the data bit read-out from one or more of the other IC's for producing a signal indicative of the parity of the combined signal. The M IC's may be interconnected to produce a system parity signal at the output of the Mth IC indicative of whether the parity of the M data bits read-out from the M IC's is correct. Each IC also includes means responsive to the system parity signal and to its internally generated first signal indicating the presence of parity errors "correcting" the selected bit outputted from the IC.
REFERENCES:
patent: 3972033 (1976-07-01), Cislaghi et al.
patent: 4038537 (1977-07-01), Cassarino, Jr. et al.
patent: 4044328 (1977-08-01), Herff
patent: 4360917 (1982-11-01), Sindelar et al.
Stewart Roger G.
Wacyk Ihor T.
Atkinson Charles E.
Haas George E.
RCA Corporation
Schanzer Henry I.
Tripoli Joseph S.
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