Tri-statable bus with apparatus to drive bus line to first level

Pulse or digital communications – Repeaters – Testing

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375 36, 375 20, 36494251, 36494206, 3649533, 3649612, 36492793, 364940, 3649408, 3649412, 364DIG2, 395800, G06F 1300, G06F 1314, G06F 1340, G06F 1342

Patent

active

050974831

ABSTRACT:
An improved high speed data transfer bus with virtual memory capability is disclosed. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. Moreover, the present invention minimizes the number of lines required to implement the bus. The present invention also minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer. Moreover, the present invention employs control signals that are driven both active and inactive, facilitating interfacing the bus to low-power CMOS technology.

REFERENCES:
patent: 3938094 (1976-02-01), Caudel
patent: 4550368 (1985-10-01), Bechtolsheim
patent: 4595923 (1986-06-01), McFarland, Jr.
patent: 4630196 (1986-12-01), Bednar, Jr. et al.
patent: 4803621 (1989-02-01), Kelly
patent: 4859877 (1989-08-01), Cooperman et al.
patent: 4945264 (1990-07-01), Lee et al.
John Uffenbeck, Microcomputers and Microprocessors: The 8080, 8085 and Z-80 Programming, Interfacing, and Troubleshooting, Prentice-Hall, 1985.

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