Bipolar semiconductor memory with recharging circuit for capacit

Details Bipolar semiconductor memory with recharging circuit for capacit Bipolar semiconductor memory with recharging circuit for capacit

1975-06-04

1977-01-25

Robinson, Thomas A.

Communications: electrical

Digital comparator systems

340173R, G11B 1140, G11C 700

Patent

active

040053938

ABSTRACT:
A bipolar semiconductor memory has a matrix of word-by-word selectable memory cells and selective circuits associated therewith in the word direction and in the bit direction for selective memory words in response to receipt of address signals. A decoder includes output switches in the form of emitter followers which are connected to respective word lines. The memory cells present capacitive loads to the lines and a recharging circuit is connected to each word line of the matrix and includes a common constant current source which is connected to each word line by way of a respective coupling element. Each of the coupling elements are embodied as base-emitter paths of recharge transistors which have the respective collectors connected directly to a respective word line. A base resistance is also connected between the respective word line and the bae of a recharge transistor.

REFERENCES:
patent: 3546682 (1970-12-01), Cagnac et al.
patent: 3786442 (1974-01-01), Alexander et al.
IBM Tech. Dis. Bull., vol. 10, No. 7, Dec. 1967, p. 1052, Andersen et al., "Circuit for Forced Recovery of Capacitive Memory Word Lines".

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