Semiconductor memory device having a plurality of memory blocks

Static information storage and retrieval – Addressing – Plural blocks or banks

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G11C 700

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050974505

ABSTRACT:
A semiconductor memory device comprises a plurality of memory blocks which are divided into a plurality of memory groups and which each include a plurality of memory cells and a plurality of word lines for selecting the memory cells, a plurality of row decoders, provided at least one for each of the memory groups, for selecting at least one of the word lines in the memory block in response to part of a word line selection address signal, and for biasing this selected word line with an input drive signal, and a drive signal generating circuit for generating a drive signal for driving the word line. This device further includes a drive signal selection circuit for selectively supplying a drive signal from the drive signal generating circuit to the row decoders corresponding to one of the memory groups specified by the remaining portion of the address signal.

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