Semiconductor memory device comprising a plurality of memory arr

Details Semiconductor memory device comprising a plurality of memory arr Semiconductor memory device comprising a plurality of memory arr

1989-11-17

1992-03-17

Hecker, Stuart N.

Static information storage and retrieval

Format or disposition of elements

365 63, 357 45, G11C 502, G11C 504, G11C 2710

Patent

active

050974408

ABSTRACT:
A semiconductor memory device comprises eight memory arrays (b 10a, 10b) arranged in one column. A peripheral circuit (60) is arranged in the central portion of the eight memory arrays (10a, 10b), two column decoders (51, 52) being arranged with the peripheral circuit (60) interposed therebetween. Each of the eight memory arrays (10a, 10b) is provided with a row decoder (20). A plurality of first column selecting lines (CL1) are provided so as to cross the three memory arrays (10a, 10b) arranged on one side of the peripheral circuit (60) from the column decoder (51). In addition, a plurality of second column selecting lines (CL2) are provided so as to intersect with the three memory arrays (10a, 10b) arranged on the other side of the peripheral circuit (60) from the column decoder (52).

REFERENCES:
patent: 4635233 (1987-01-01), Matsumoto et al.
patent: 4660174 (1987-04-01), Takemae et al.
patent: 4779227 (1988-10-01), Kurafuji et al.
patent: 4849943 (1989-07-01), Pfennings
Kiyoto Ohta et al., "A 1-Mbit Dram with 33-MHz Serial I/O Ports", IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 649-654.
Kimura et al., "Power Reduction Techniques in Megabit DRAMs", IEEE Journal of solid-State Circuits, vol. SC-21, No. 3, Jun. '86.

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