High speed dividing apparatus

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G06F 752

Patent

active

050974351

ABSTRACT:
An operation apparatus and method receive a dividend and a divisor as the input values of a divide operation processing, repeat a subtractive operation when the dividend and divisor are determined as being equal in sign to each other, and progress the repetition of an additive operation when the dividend and divisor are determined as being different in sign from each other. When the most significant bit of a quotient is calculated as having a negative number upon the sign equality of the dividend and divisor and when the most significant bit of the quotient is calculated as having a negative number upon the sign inequality of the dividend and divisor, an overflow is repeated at a time the other quotient bit conincides with the most significant bit of the quotient to detect it during a portion of the operation process.

REFERENCES:
patent: 4272827 (1981-06-01), Inui et al.
patent: 4872214 (1989-10-01), Zurawski
patent: 4891780 (1990-01-01), Miyoshi
IEEE Transaction Computers, vol. 17, No. 10, Oct. 1968, "Higher Estimates of the Divisor and Partial Reminders"; Atkins, D. E.; 1968.

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