Pipeline processor with hardware loop function using instruction

Details Pipeline processor with hardware loop function using instruction Pipeline processor with hardware loop function using instruction

1994-12-23

1996-04-09

An, Meng-Ai

Boots, shoes, and leggings

3642318, 3642443, 364251, 3642511, 3642592, 3642613, 364262, 3642621, 3642624, 364DIG1, G06F 900, G06F 940

Patent

active

055070272

ABSTRACT:
A pipeline processor having a hardware loop function, and having transfer paths L14 and L13 which directly transfer a value of a flag register 10 being set according to the results of the operations to a loop control unit 11, and so configured that the loop control unit 11 reads the value of the flag register 10 via the transfer paths L14 and L13 and terminates a loop processing when it is the predetermined value. The loop processing can be terminated without adversely affecting the data processing efficiency when a conditional jump instruction is executed during the loop processing, and operations, data transfers and other processings can be executed other than a loop-escaping operation.

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Tirumalai et al; "Parallelization of Loops with exist on Pipelined Architectures" Hewlett-Packard Laboratories; IEEE May 1990.

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