Excavating
Patent
1991-08-27
1995-01-24
Cosimano, Edward R.
Excavating
364579, G06F 1520
Patent
active
053847849
ABSTRACT:
A semiconductor memory device includes a memory array. The bit line pairs of the odd number order in the memory array belong to a first group, and the bit line pairs of the even number order belong to a second group. A first amplifier is connected to each bit line pair. Corresponding to the first group, write buses read buses and a read/test circuit are provided. Corresponding to the second group, write buses read buses and a read/test circuit are provided. A column decoder selects a plurality of bit line pairs simultaneously at the time of testing. At the time of testing, each of the read/test circuits compares data read out from the plurality of bit line pairs belonging to the corresponding group with a given expected data for providing the comparison result.
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Kikuda Shigeru
Kinoshita Mitsuya
Miyamoto Hiroshi
Mori Shigeru
Morooka Yoshikazu
Cosimano Edward R.
Mitsubishi Denki & Kabushiki Kaisha
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