Sequential network optimization designing apparatus

Details Sequential network optimization designing apparatus Sequential network optimization designing apparatus

1996-05-15

1998-06-02

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364490, G06F 1750

Patent

active

057614873

ABSTRACT:
A sequential network optimization designing apparatus which can reduce the circuit scale of an object circuit taking the circuit logic across flip-flops into consideration without moving the flip-flops, and which can reduce the number of flip-flops of the object circuit. A subgraph extraction section extracts a subgraph from a flip-flop information attached transitive implication graph produced by a flip-flop information attached transitive implication graph production section. A subgraph transformation section transforms the subgraph so as to decrease the number of edges and the number of flip-flops of the subgraph. A subnetwork addition section generates a subnetwork corresponding to the transformed subgraph and adds the subnetwork to the sequential network. A redundancy removal section removes redundancies created in the sequential network by the addition of the subnetwork.

REFERENCES:
patent: 5461573 (1995-10-01), Chakradhar et al.
Touati et al., "Computing the Initial States of Retimed Circuits", IEEE, 1993, pp. 157-162.
Ashar et al., "Implied State Transition Graphs: Applications to Sequential Logic Synthesis and Test", IEEE, 1990, pp. 84-87.
Sentovich et al., "Sequential Circuit Design Using Synthesis and Optimization", IEEE, 1992, pp. 328-333.
S. Malik et al., "Retiming and Resynthesis: Optimizing Sequential Networks with Combinational Techniques", IEEE Transactions on Computer-Aided Design, vol. 10, No. 1, Jan. 1991, pp. 74-84.
M. Yuguchi et al., "Multi-Level Logic Minimization Based on Multi-Signal Implications", 32nd Design Automation Conference, Jun. 1995, pp. 658-662.
G. De Micheli, "Synchronous Logic Synthesis: Algorithms for Cycle-Time Minimization", IEEE Transactions on Computer-Aided Design, vol. 10, No. 1, Jan. 1991, pp. 63-73.
L. Entrena et al., "Sequential Logic Optimization by Redundancy Addition and Removal", IEEE, 1993, pp. 310-315.

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