Patent
1994-09-12
1998-06-02
Kim, Ken S.
39518214, 395555, 395800, G06F 938
Patent
active
057614679
ABSTRACT:
The microprocessor which processes instructions with commit conditions in parallel includes a sequential register file for storing result data of sequential instructions; a shadow register file for storing result data of speculative instructions; a TF register including a plurality of entries each holding information indicating that the commit condition is "true", "false" or "undetermined"; an execution control circuit for comparing the commit condition and a corresponding entry in TF register, storing the result data in sequential register file if the instruction is sequential, and storing the result data in shadow register file if the instruction is the speculative; and a commit control circuit for storing the commit condition and transferring the result data stored in the shadow register file to sequential register file when a coincidence is found between true/false for the commit condition and true/false in TF register 10.
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Kim Ken S.
Mitsubishi Denki & Kabushiki Kaisha
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