Nonrestoring divider

Details Nonrestoring divider Nonrestoring divider

1985-04-02

1988-01-26

Malzahn, David M.

Boots, shoes, and leggings

G06F 752

Patent

active

047220694

ABSTRACT:
A divider apparatus includes a divisor register for storing a divisor, a partial remainder register for storing a dividend or a partial remainder, a predictor for predicting a partial quotient, a multiplier for multiplying the content of the divisor register, and a first adder for subtracting the output of the multiplier from the content of the partial remainder register and for calculating the partial remainder. The divider apparatus further includes a second adder for determining the difference between the upper digits of the multiplier and the upper digits of the partial remainder register, a first predictor for predicting the partial quotient from the output of the first adder and the upper digits of the divisor register, a second predictor for predicting the partial quotient in the third cycle from a corrected output of the second adder and the digits of the divisor register, a carry predictor for determining the carry to be propagated to the second adder from remaining digits of the multiplier and remaining digits of the partial remainder register, and a selector for selecting one of outputs of the first predicting circuit and the second predictor in dependence upon the output of the carry predictor.

REFERENCES:
patent: 3852581 (1974-12-01), Reynard
patent: 4320464 (1982-03-01), Desmonds
Saltman, "Reducing Computing Time for Synchronous Binary Division", IRE Trans. on Electronic Computers, Jun. 1961, pp. 169-174.
Kai Hwang; Computer Arithmetic, Chapter 7, .COPYRGT.1979, by John Wiley & Sons, Inc.

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