Method and apparatus for implementing modulo arithmetic calculat

Details Method and apparatus for implementing modulo arithmetic calculat Method and apparatus for implementing modulo arithmetic calculat

1985-03-25

1988-01-26

Malzahn, David H.

Boots, shoes, and leggings

G06F 772

Patent

active

047220678

ABSTRACT:
A modulo arithmetic unit and method for providing a sum of first and second numbers is provided. In one form, a first adder calculates a first sum which is equal to the arithmetic sum of the first and second numbers. A second adder is provided for adding the first number to an offset value equal to (2.sup.X -M), where X defines the number of bits of the number system used, M is a predetermined modulus and X and M are integers. A third adder operates in parallel with the first adder to calculate the sum of the output value of the second adder and the second operand to provide a second output sum and a carry output bit. In another form, only two adders are utilized wherein the first adder calculates a first output sum of the first and second numbers, and the second adder calculates the sum of the first output sum and the offset value. Both illustrated forms utilize a multiplexer which outputs one of the two calculated output sums depending upon whether a wraparound of an upper modulus boundary occurred.

REFERENCES:
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patent: 4598266 (1986-07-01), Bernardson
"DSP Microprocessor ADSP-2100", Analog Devices Inc., pp. 1-35, Aug. 1986.
Roesgen et al., "Moving Memory Off Chip, DSP .mu.P Squeezes in More Computation Power", Electronic Design, pp. 131-140, Feb. 20, 1986.
Garde et al., "16-Bit-Slice Family Creates Ultrafast Digital Signal Processors", Electronic Design, May 17, 1984, pp. 136-144.
Raminarayan, "Practical Realisation of mod, p,p Prime Multiplier", Electronics Letters, Jun. 5, 1980, vol. 16, No. 12, pp. 466-467.

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