Method of manufacturing an integrated circuit device having vert

Details Method of manufacturing an integrated circuit device having vert Method of manufacturing an integrated circuit device having vert

1980-09-02

1984-05-22

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576W, 29577C, 29578, 29580, 357 43, 357 55, 148187, H01L 2195

Patent

active

044492847

ABSTRACT:
A method of manufacturing an integrated circuit device including vertical static induction transistors (SIT) having a first recess between the gate region and the drain (or source) region to reduce the capacitance between both regions and a second recess on an outer surface of the SIT gate to reduce the gate capacitance and a minority carrier storage. The method includes the steps of removing a masking film on the SIT channel region while leaving the masking film at the portions of the gate region and the drain region; forming the first and the second recesses in the channel region; locally oxidizing the exposed channel region; and forming the gate region and the drain region by removing the masking film.

REFERENCES:
patent: 4008107 (1977-02-01), Hayasaka et al.
patent: 4284999 (1981-08-01), Iwanami

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