Power down system and method for pipelined logic functions

Details Power down system and method for pipelined logic functions Power down system and method for pipelined logic functions

1995-08-21

1999-11-09

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Architecture based instruction processing

712 1, 713323, 713601, G06F 938

Patent

active

059833394

ABSTRACT:
Logic circuitry added to each stage of a pipeline of staged logic circuitry sequentially removes a clock signal from each stage when data incoming to the pipeline is invalid, or not to be processed for any practical use. The same logic circuitry is also useful for reapplying the clock signal to the successive stages of the pipeline when valid data is to be processed by the pipeline.

REFERENCES:
patent: 4317180 (1982-02-01), Lies
patent: 4685058 (1987-08-01), Lee et al.
patent: 4736119 (1988-04-01), Chen et al.
patent: 4956618 (1990-09-01), Ulmer
patent: 5025387 (1991-06-01), Frane
patent: 5167024 (1992-11-01), Smith et al.
patent: 5218704 (1993-06-01), Watts, Jr. et al.
patent: 5377205 (1994-12-01), Shi
patent: 5418969 (1995-05-01), Matsuzaki et al.
patent: 5457781 (1995-10-01), Millar et al.
patent: 5551017 (1996-08-01), Baxter
patent: 5586332 (1996-12-01), Jain et al.
patent: 5603012 (1997-02-01), Sotheran
patent: 5708374 (1998-01-01), Durham et al.
patent: 5732233 (1998-03-01), Klim et al.

Affiliated with

Also associated with

Rating

Power down system and method for pipelined logic functions does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Power down system and method for pipelined logic functions, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power down system and method for pipelined logic functions will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1470452