Computer system having organization for multiple condition code

Details Computer system having organization for multiple condition code Computer system having organization for multiple condition code

1997-04-30

1999-11-09

Donaghue, Larry D.

Electrical computers and digital processing systems: processing

Processing architecture

Superscalar

712217, 712216, 712215, G06F 1500

Patent

active

059833351

ABSTRACT:
Computer system with multiple, out-of-order, instruction issuing system suitable for superscalar processors with a RISC organization, also has a Fast Dispatch Stack (FDS), a dynamic instruction scheduling system that may issue multiple, out-of-order, instructions each cycle to functional units as dependencies allow. The basic issuing mechanism supports a short cycle time and its capabilities are augmented. Condition code dependent instructions issue in multiples and out-of-order. A fast register renaming scheme is presented. An instruction squashing technique enables fast precise interrupts and branch prediction. Instructions preceding and following one or more predicted conditional branch instructions may issue out-of-order and concurrently. The effects of executed instructions following an incorrectly predicted branch instruction or an instruction that causes a precise interrupt are undone in one machine cycle.

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