Programmable hold-off for integrated circuit I/O pins

Details Programmable hold-off for integrated circuit I/O pins Programmable hold-off for integrated circuit I/O pins

1993-04-13

1995-01-24

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327261, H03K 3289

Patent

active

053844947

ABSTRACT:
A programmable hold-off circuit for an integrated circuit for selectively providing hold-off for outputs of the integrated circuit. The programmable hold-off circuit includes a hold-off latch for receiving an output signal from the interior logic of the integrated circuit, and for providing a hold-off latch output, an output buffer responsive to hold-off latch output for providing a buffered output, a hold-off control circuit responsive to a hold clock for controlling the hold-off latch to be continuously transparent when the hold-off control circuit is programmed for no hold-off, and for controlling the hold-off latch pursuant to the hold clock when the hold-off control circuit is programmed for hold-off. The hold-off control circuit is programmed, for example, pursuant to a boundary scan flip-flop.

REFERENCES:
patent: 4864161 (1989-09-01), Norman et al.
patent: 4926451 (1990-05-01), Yoshihara et al.
patent: 5015875 (1991-05-01), Giles et al.
patent: 5124573 (1992-05-01), Wong
patent: 5130568 (1992-07-01), Miller et al.
patent: 5148052 (1992-09-01), Yellamilli
patent: 5175447 (1992-12-01), Kawasaki et al.
patent: 5216302 (1993-06-01), Tanizawa
patent: 5257223 (1993-10-01), Dervisoglu
patent: 5281864 (1994-01-01), Hahn et al.

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