Scan based path delay testing of integrated circuits containing

Details Scan based path delay testing of integrated circuits containing Scan based path delay testing of integrated circuits containing

1997-07-07

1998-06-02

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

057612153

ABSTRACT:
Accurate delay testing of integrated circuits containing memory arrays embedded in combinational logic utilizes actual memory array timing. Actual memory timing signals provide the timing for bypassing the memory in SCAN Mode. The result is that simulated memory accesses during SCAN Mode testing have the same timing as actual memory accesses have during functional mode operation. Thus delay testing during SCAN Mode through paths containing both combinational logic and memory arrays accurately determines path delays.

REFERENCES:
patent: 5068603 (1991-11-01), Mahoney
patent: 5592493 (1997-01-01), Crouch et al.

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