Synchronous memory with pipelined write operation

Details Synchronous memory with pipelined write operation Synchronous memory with pipelined write operation

1996-05-21

1998-06-02

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

36518912, 36523008, 365194, G11C 800, G11C 700

Patent

active

057611505

ABSTRACT:
There is provided a method of controlling an internal address signal of an RAM in which a late-write method is realized on a chip. Two sets of address registers for reading and writing are provided for each address and further a middle register is provided between the two sets of address registers. The middle register is controlled by a signal formed by obtaining the AND result of a clock signal and a write enable signal and the two sets of address registers for reading and writing are controlled only by the clock signal. A selection circuit selects outputs of the two sets of address registers as an input in accordance with the write enable signal to control an internal address.

REFERENCES:
patent: 5587961 (1996-12-01), Wright et al.

Affiliated with

Also associated with

Rating

Synchronous memory with pipelined write operation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous memory with pipelined write operation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous memory with pipelined write operation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1468960