Semiconductor memory device with program/erase verification

Details Semiconductor memory device with program/erase verification Semiconductor memory device with program/erase verification

1996-11-15

1998-06-02

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518522, 36518529, 365218, G11C 1606, G11C 1604, G11C 700

Patent

active

057611220

ABSTRACT:
A semiconductor memory device includes a semiconductor substrate, a memory cell array having memory cells, each of which stores data, formed in matrix on the semiconductor substrate, a plurality of data latch circuits, each, of which is arranged at one end of at least one bit line connected to the memory cell array and for latching programming data, a control section for judging whether all of a plurality of latched data included in date latch groups constituted by the plurality of data latch circuits are the same as a first data or not and for controlling to change a potential of a plurality of first nodes according to the judging result, a section for detecting potentials of the plurality of the first nodes and for judging whether all data latched by the latch circuits are the same as the first data and for controlling to change a potential of a plurality of second nodes according to the judging result, and a section for detecting the potential of the plurality of second nodes and for outputting a judging result whether all of data latched by data latch circuits, are the same as the first data or not.

REFERENCES:
patent: 5361227 (1994-11-01), Tanaka et al.
patent: 5610859 (1997-03-01), Nakamura et al.
patent: 5627782 (1997-05-01), Tanaka et al.

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