Method and apparatus for improving the speed of a logic circuit

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G06F 750

Patent

active

057611076

ABSTRACT:
The invention is disclosed as embodied in a data processing system circuit for outputting a signal based on an evaluation of input signals coupled to the circuit. The circuit has a number of transistors configured so that the output signal is triggered by a triggering combination of input signals. The circuit also has a discharge transistor coupled to a signal for switching the discharge transistor to a state tending to discharge a node in the circuit. The node must be discharged to a certain level to trigger the output signal, so that discharging the node after it has become charged up above the certain level tends to reduce evaluation time for the circuit.

REFERENCES:
patent: 4559609 (1985-12-01), Robinson, Jr. et al.
patent: 4970677 (1990-11-01), Young
patent: 4989174 (1991-01-01), Gardei
patent: 4999804 (1991-03-01), Nukiyama
patent: 5148387 (1992-09-01), Yano et al.
patent: 5406506 (1995-04-01), Jiasheng et al.

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