Boots – shoes – and leggings
Patent
1997-03-06
1998-06-02
Teska, Kevin J.
Boots, shoes, and leggings
364578, G06F 1560
Patent
active
057610762
ABSTRACT:
The sum of capacitance is determined by an LSI load characteristic extraction program 217, as for the capacitance of a plurality of wiring patterns constituting different segments of a wiring, between the wiring and a plurality of other wiring patterns adjacent to the wiring, and the resistance of each wiring pattern also is determined. On the basis of the resistance and capacitance, a load characteristic value 222 comprised of a plurality of predetermined lower order coefficients of series expansion of complex admittance at the driving point of that wiring is calculated. A delay calculation program 223 calculates delay time and power dissipation as the driving characteristic of logic gates which drive this wiring, according to the coefficients and a device characteristic library 212. The library 212 is generated in advance by a program 600, in which a plurality or lower order coefficients of series expansion obtained by series expanding the complex admittance of a plurality of wirings of different length, the delay time and power dissipation of a device when driving these wirings by that device are maintained. For evaluating the capacitance of respective wiring patterns, by dividing the substrate into a plurality of regions, using a region management table for registering a plurality of wiring patterns for each region, and detecting wiring patterns in the same region, the capacitance therebetween is calculated.
REFERENCES:
patent: 5295088 (1994-03-01), Hartoog et al.
patent: 5359535 (1994-10-01), Djaja
patent: 5404310 (1995-04-01), Mitsuhasi
patent: 5446674 (1995-08-01), Ikeda et al.
patent: 5452224 (1995-09-01), Smith, Jr. et al.
"Modeling the Driving Point Characteristic of Resistive Interconnect for Accurate Delay Estimation" O'Brien, 1989 IEEE pp. 512-515.
"Laxter, A New Method for Extraction of Parasitic Effects from MCM Layout," A. Simsek et al., IEEE, Apr. 1994, pp. 344-347.
"A Model for Verification of Coupled High-Speed Packages and Interconnects," A. Simsek et al., IEEE, May 1993, pp. 538-541.
"Delay Modeling for GaAs DCFL Circuits," A. Kayss. et al., IEEE, GaASICS Symposium, Mar. 1993, pp. 67-70.
"Combined Topological and Functionality Based Delay Estimation Using a Layout Driven Approach for High Level Applications," C. Ramachandran et al., IEEE, Aug. 1992, pp. 72-78.
"Interconnection Delay In Very High-Speed VLSI," D. Zhou et al., IEEE, Jul. 1991, pp. 779-790.
"A New Efficient Algorithm for Analysis of Piecewise-Linear Resistive Circuits," Q. Huang et al., IEEE, 1989, pp. 2169-2172.
"Modeling the Driving-Point Characteristics of Resistive Interconnect for Accurate Delay Estimation," P. O'Brien et al., IEEE 1989, pp. 512-515.
Hitachi , Ltd.
Roberts A. S.
Teska Kevin J.
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