Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1988-11-10
1990-01-09
Miller, Stanley D.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307443, 307445, 307448, 307465, 307469, 364716, H03K 1920, G06F 738
Patent
active
048930318
ABSTRACT:
Two basic logical circuits having a transfer gate section consisting of a channel MOS transistor and a P-channel MOS transistor, the gate electrode of the former being connected to a first input terminal to which a first input signal is applied, the gate electrode of the latter being connected to a second input terminal, the source electrodes of the N-channel and P-channel MOS transistors connected in parallel being connected to a third input terminal to which a third input signal is applied, and either a P-channel MOS switching transistor or a N-channel MOS transistsor. When the P-channel MOS transistor is used as the switching transistor, its gate electrode is connected to the first input terminal and the remaining electrodes are connected to an output terminal and the second input terminal, thereby realizing either NAND operation or OR operation by the same circuit construction but in accordance with the combination of the three input signals. On the other hand, when the N-channel MOS transistor is used as the switching transistor, its gate electrode is connected to the second input terminal and the remaining electrodes thereof are connected to the output terminal and the first input terminal, thereby realizing either AND or NOR operation by the same circuit construction but in accordance with the different combination of the three input signals applied to the three imput terminals.
REFERENCES:
patent: 4567385 (1986-01-01), Falater et al.
patent: 4652777 (1987-03-01), Cline
Balasubramanian, "Increasing Chip Density by Space Sharing of Programmed Logic Arrays", IBM Technical Disclosure Bulletin, vol. 20, No. 10, Mar. 1978, pp. 4016-4018.
Hiltelbeitel, "Two-Device CMOS Logic Functions", IBM Technical Disclosure Bulletin, vol. 27, No. 6, Nov. 1984, p. 3346.
Kabushiki Kaisha Toshiba
Miller Stanley D.
Phan Trong Quang
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