Synchronous DRAM whose power consumption is minimized

Details Synchronous DRAM whose power consumption is minimized Synchronous DRAM whose power consumption is minimized

1997-08-29

2000-01-11

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

365191, G11C 800

Patent

active

060143398

ABSTRACT:
An SDRAM that can operate quickly and requires a small amount of power. The SDRAM is a synchronous DRAM operating synchronously with an externally-input clock and has a clock buffer for generating an operation clock using the external clock, a plurality of pipelines, and gates interposed among the pipelines, operating according to the operation clock so as to restrict the timing of inputting an output of a previous stage to a subsequent stage. The synchronous DRAM, in which at least part of operations to be carried out consecutively are pipelined, further has an operation command judgment circuit for determining from the operating state of the synchronous DRAM whether or not the pipelines should be operated, and gate control circuits for giving control so that only when the operation command judgment circuit determines that the pipelines should be operated, is the operation clock supplied to the gates.

REFERENCES:
patent: 5384737 (1995-01-01), Childs et al.
patent: 5550781 (1996-08-01), Takai

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