Control apparatus for a plurality of memory units

Details Control apparatus for a plurality of memory units Control apparatus for a plurality of memory units

1982-05-11

1984-12-11

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1100

Patent

active

044882238

ABSTRACT:
In a data processing system of the type having a processor and a plurality of memory units, which can be accessed simultaneously by the processor, the processor writes simultaneously into both memory units and reads from a particular one of the memory units except when the particular memory unit exhibits an error condition in which case writing and reading are performed in a different memory unit. The switching from the master memory unit to an alternate memory is performed simultaneously with the error indication in the master memory unit during a write operation and is performed at the next clock pulse in a read operation so that a retry can be performed.

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patent: 4044337 (1977-08-01), Hicks et al.
patent: 4089063 (1978-05-01), Takezono et al.

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