Synchronizing circuit for a television receiver

Facsimile and static presentation processing – Static presentation processing – Attribute control

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Details

358158, 358148, H04N 949, H04N 512, H04N 504

Patent

active

044881703

ABSTRACT:
A synchronizing circuit arrangement for a television receiver having an oscillator which generates a clock signal the frequency of which is substantially higher than the line frequency and having a frequency dividing circuit which derives signals of the line frequency from the clock frequency by means of division. During a predetermined number of line periods a phase comparison stage determines the average value of the phase deviation between the received line synchronizing signal and a reference signal of the line frequency and applies the value obtained to a preset stage for adjusting in a subsequent time interval, for example one line period during the field blanking interval, the divisor by which the frequency dividing circuit divides the clock frequency. The clock frequency may be a multiple of the chrominance subcarrier frequency, in which case the oscillator is continuously readjusted by the phase comparison stage when the color killer circuit is operative, while the divisor is not changed.

REFERENCES:
patent: 3904823 (1975-09-01), Van Straaten
patent: 4025951 (1977-05-01), Eckenbrecht
patent: 4351002 (1982-09-01), Decraemer

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