Multilayer metal silicide interconnections for integrated circui

Details Multilayer metal silicide interconnections for integrated circui Multilayer metal silicide interconnections for integrated circui

1983-04-11

1984-12-11

James, Andrew J.

357 59, 357 65, 357 67, H01L 2354, H01L 21283, H01L 2144

Patent

active

044881665

ABSTRACT:
A process and resulting structure are disclosed for forming vias in integrated circuit structures using metal silicide interconnections. A lower conductor is formed by sequentially depositing silicon and a refractory metal which reacts with the silicon to create a layer of metal silicide. A subsequent layer of silicon is deposited on the surface of the metal silicide. This layer of silicon is insulated from overlying layers by forming insulating material over desired regions of the layer of silicon. A second layer of metal is then deposited across the structure. In openings in the insulating material the metal reacts with the second layer of silicon to form a via of metal silicide. A final layer of silicon may be deposited to convert any remaining metal in the second layer of metal to metal silicide, and the structure annealed to lower its resistivity.

REFERENCES:
patent: 4128670 (1978-12-01), Gaensslen
patent: 4285761 (1981-08-01), Fatula, Jr. et al.
patent: 4329706 (1982-05-01), Crowder et al.
patent: 4392150 (1983-07-01), Courreges
"Method of Fabricating MOSFET Integrated Circuits with Low Resistivity Interconnection Lines"-Rideout-IBM Technical Disclosure Bulletin, vol. 23, No. 6, Nov. 1980, pp. 2563-2566.
"Fabrication of Vias in a Multilayered Metallization in LSI Technology"-Laibowitz et al.-IBM Technical Disclosure Bulletin, vol. 21, No. 12, May 1979, pp. 5051-5052.

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