Swallow counter with modulus signal output control

Electrical pulse counters – pulse dividers – or shift registers: c – Applications – Control

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Details

377 54, 377111, 377114, G06M 300

Patent

active

059828404

ABSTRACT:
Improved PLL frequency synthesizer circuits, including a novel swallow counter, may be operated at high speeds without experiencing internal delays or malfunctions. The swallow counter supplies a modulus signal to a prescaler which is capable of selectively changing a frequency-dividing ratio of a frequency signal. The swallow counter includes a shift register, a counter, a count-up detector, a modulus signal generator, and a control circuit. The swallow counter is connected to the prescaler and the program counter, and is capable of counting a frequency-divided signal based on a set value data and producing the modulus signal in response to a load signal after counting is completed. The swallow counter supplies the modulus signal to the prescaler and determines whether the set value data is data prepared to fix the frequency-dividing ratio. If the set value data is data for fixing the frequency-dividing ratio, the swallow counter operates in such a manner so as to restrict supply of the modulus signal, originated from the set value data, to the prescaler. The swallow counter may be included in a comparison frequency divider for supplying a comparison signal to a phase comparator in a PLL frequency synthesizer circuit that includes a voltage controlled oscillator.

REFERENCES:
patent: 4184068 (1980-01-01), Washburn
patent: 4545063 (1985-10-01), Kamimaru
patent: 5534821 (1996-07-01), Akiyama et al.
patent: 5572168 (1996-11-01), Kasturia
patent: 5790625 (1998-08-01), Arimilli

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