Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Patent
1998-03-23
1999-11-09
Nelms, David
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
36518905, 36518911, 365227, G11C 800
Patent
active
059827050
ABSTRACT:
An output transistor in an output buffer in a semiconductor memory device is formed in a well region which is electrically isolated from the substrate by a triple well structure. When the output transistor conducts, the potential of the well in which the output transistor is formed is controlled to follow the source potential of the output transistor, so that the increase in the threshold voltage caused by a substrate biasing effect can be prevented, and larger output current results.
REFERENCES:
patent: 4707625 (1987-11-01), Yanagisawa
patent: 5543734 (1996-08-01), Volk et al.
patent: 5559464 (1996-09-01), Orii et al.
patent: 5847595 (1998-12-01), Kono et al.
Le Thong
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
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