Non-volatile memory device

Details Non-volatile memory device Non-volatile memory device

1998-11-20

1999-11-09

Mai, Son

Static information storage and retrieval

Floating gate

Particular biasing

36518522, 36518524, G11C 1604

Patent

active

059826703

ABSTRACT:
The present invention is a non-volatile memory device, wherein programming or erasing of memory cells is carried out by injecting or removing carriers in floating gates in the memory cells, comprising: a plurality of memory blocks each comprising a plurality of memory cells, respectively; and an erasing circuit for applying an erasing stress in units of the memory blocks and verifying that erasure has been completed in units of memory cells; wherein the erasing circuit applies an erasing stress to the plurality of memory blocks simultaneously until a past erasing stress minimum value for the plurality of memory blocks. According to the aforementioned invention, an erasing stress value, such as a number of erasing stress applications, is recorded for each memory block in past erasing operations, and the minimum erasing stress value of these erasing stress values is recorded. In the next erasing operation, an erasing stress is applied to a plurality of memory blocks in one batch, until this minimum erasing stress value is reached. Therefore, the erasing time can be shortened in comparison with a conventional method where application of erasing stress and erasure verification are repeated for each memory block, after respectively.

REFERENCES:
patent: 5579262 (1996-11-01), Song
patent: 5646891 (1997-07-01), Okamoto
patent: 5841721 (1998-11-01), Kwon et al.
patent: 5844842 (1998-12-01), Seki et al.

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