Sense amplifier circuit for semiconductor memory devices

Details Sense amplifier circuit for semiconductor memory devices Sense amplifier circuit for semiconductor memory devices

1998-01-26

1999-11-09

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

3651852, 36518513, 36518901, 36518909, G11C 1606

Patent

active

059826665

ABSTRACT:
A sense amplifier circuit for a semiconductor memory device comprises first current/voltage conversion means for converting a current of a memory cell to be read into a voltage signal, second current voltage/conversion means for converting a reference current into a reference voltage signal, and voltage comparator means for comparing the voltage signal with the reference voltage signal. The sense amplifier circuit comprises capacitive decoupling means for decoupling the voltage signal from the comparator means, and means for providing the capacitive decoupling means with an electric charge suitable for compensating an offset voltage introduced in the voltage signal by an offset current superimposed on the current of the memory cell to be read.

REFERENCES:
patent: 4264872 (1981-04-01), Suzuki
patent: 5289419 (1994-02-01), Hashizumi et al.
patent: 5305273 (1994-04-01), Jinbo
patent: 5729492 (1998-03-01), Campardo
Terada, Y. et al., "120-ns 128 K .times.8-bit / 64K .times.16-bit CMOS EEPROM's", IEEE Journal of Solid-State Circuits24:1244-1249, Oct. 1989.
Masuoka, F. et al., "A 256-kbit Flash E.sup.2 PROM Using Triple-Polysilicon Technology," IEEE Journal of Solid-State Circuits 22:548-552, Aug. 1987.

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