Patent
1995-12-19
1998-12-15
Sheikh, Ayaz R.
395737, G06F 946
Patent
active
058505580
ABSTRACT:
A programmable interrupt controller is provided for use in computer systems including one or more CPUs. The programmable interrupt controller includes an interrupt request interface, a storage device, and at least one processor interface having an interrupt nesting buffer. An unique interrupt identification code is assigned to each interrupt request and used to reference information in the storage device associated with each interrupt request. The interrupt request interface uses the unique interrupt identification code to access the information for each interrupt request and determine if the interrupt request should proceed to one of the processor interfaces. The processor interface uses the unique interrupt identification code to access the information in order to determine if and when the interrupt request should issue to one of the CPUs.
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Intel MultiProcessor Specification Version 1.1, Apr. 1994, pp. 1-54.
Bailey Joseph A.
Mudgett Dan S.
Qureshi Qadeer A.
Advanced Micro Devices
Kivlin B. Noel
Pancholi Jigar
Sheikh Ayaz R.
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