System and method for validating interrupts before presentation

Details System and method for validating interrupts before presentation System and method for validating interrupts before presentation

1995-12-19

1998-12-15

Sheikh, Ayaz R.

395734, 395735, 395736, 395737, 395738, 395739, 395740, 395741, 395742, 395868, 395869, 395870, 395871, G06F 1300, G06F 1314

Patent

active

058505555

ABSTRACT:
A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a validity checker, and at least one processor interface. The validity checker monitors the state of each interrupt request as it is processed through the interrupt controller. The interrupt request is canceled if the interrupt request becomes invalid. Alternatively, the programmable interrupt controller issues a spurious interrupt vector if the interrupt request becomes invalid after a CPU has responded.

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Intel MultiProcessor Specification Version 1.1, Apr. 1994, pp. 1-54.

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