Code translation circuit for converting a binary data to a binar

Details Code translation circuit for converting a binary data to a binar Code translation circuit for converting a binary data to a binar

1997-07-11

1999-11-09

Young, Brian

Coded data generation or conversion

Digital code to digital code converters

To or from mixed base codes

341 85, H03M 712

Patent

active

059823070

ABSTRACT:
The first shift-register 1 has 4 bits.times.N stages for storing the operated result BCD data 4 bits by 4 bits from LSD. The second shift-register 2 has 4 bits.times.M stages for storing a BIN data to be translated 4 bits by 4 bits from MSD. The D-F/F 5 is to store the output from the first shift-register 1 and the intermediate result, and output thereof is supplied to the arithmetic/logic circuit 6 through the first selector 3. The output of the second shift-register 2 is selected by the second selector 4 to be supplied to the arithmetic/logic circuit 6. The arithmetic/logic circuit 6 performs.times.16 operation for the stored data in the shift register 1, and adding the resultant to 4 bits data stored in the shift-register 2 with carry process. The output DO of the arithmetic/logic circuit 6 is stored in the D-F/F 5 in the first half of the shift clock SCK1, and stored in the shift-register 1 in the latter half of the shift clock SCK1. The shift-register 1 makes a round, while the shift-register 2 is 1 stage shifted.

REFERENCES:
patent: 3564225 (1971-02-01), Watson, Jr.
patent: 3624374 (1971-11-01), Steiner
patent: 4068227 (1978-01-01), Graham
patent: 4069478 (1978-01-01), Miller
patent: 4103234 (1978-07-01), Frazier, Jr.

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