Sense amplifier for integrated memory array

Details Sense amplifier for integrated memory array Sense amplifier for integrated memory array

1981-05-05

1983-03-01

Chatmon, Jr., Saxfield

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072382, 3072388, 307581, 307574, 365205, 365206, G11C 706, G01R 19165, H03K 524, H03K 508

Patent

active

043756000

ABSTRACT:
A memory-array sense amplifier includes a grounded-gate depletion-mode FET connected between a bit line and a sense node. Another FET connects a supply voltage VDD to the sense node when turned on by a clock phase signal. Further FETs form a latch circuit.

REFERENCES:
patent: 3588848 (1971-06-01), Van Beek
patent: 3846643 (1974-11-01), Chu et al.
patent: 4004170 (1977-01-01), Henke
patent: 4053873 (1977-10-01), Freeman et al.
patent: 4081699 (1978-03-01), Hirt et al.
patent: 4082966 (1978-04-01), Lou
patent: 4270189 (1981-05-01), Brossard et al.
IBM Technical Disclosure Bulletin, vol. 17, No. 4 Sep. 1974, "Read-Only Storage Bit Precharge/Sense Circuit", Cordaro.
IBM Technical Disclosure Bulletin, vol. 23, No. 7A, Dec. 1980 "Sense Amplifier with Resistive Decoupling of Bit Lines", Schuster.
IBM Technical Disclosure Bulletin, vol. 22, No. 11, Apr. 1980 "Sense Latch with Adjusting Series Impedance", Anderson.
IBM Technical Disclosure Bulletin, vol. 24, No. 10, Mar. 1982 "Differential Sense Amplifier for Unbalanced Data Lines" Tien.

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