1992-12-09
1996-04-09
Auve, Glenn A.
395729, G06F 1300
Patent
active
055069703
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to an MCA bus arbitrator integrated circuit that provides an interface between an MCA bus and the logic circuits of a card on which various functions have been incremented.
BACKGROUND OF THE INVENTION
As is known in the art microchannel bus arbiter circuits are used to connect a peripheral device to a microchannel bus. The arbiter circuit typically includes a bus arbitration logic circuit, a command logic circuit, a decode circuit, and a plurality of programmable option select (POS) registers. The arbiter circuits further include multi functions pins and a plurality of comparators coupled to selected ones of the POS registers and coupled to selected groups of pins of the multi functions pins. The multifunction pins may be provided as read and write signal entry pins and are used to decide whether or not the POS registers can be used internally or externally on these multi-function pins.
It would be desirable, however, to provide output pins for each of the arbitration logic, command logic, and decode circuits the meaning of which could be changed according to the content of the POS registers and the selected mode for enabling, for example, several kinds of memory, such as Random Access Memory (RAM) and Read Only Memory (ROM).
SUMMARY OF THE INVENTION
The present invention relates to an MCA bus arbitrator integrated circuit that provides an interface between an MCA bus and the logic circuits of a card on which various functions have been incremented.
Hence a first goal of the invention is to provide a bus arbitrator integrated circuit allowing various operating modes of this integrated circuit to be implemented.
This goal is achieved by the fact that the integrated circuit comprises a bus arbitration logic, a command logic, a decode circuit, a set of registers, and a logic circuit decoding the signals received to determine one operating mode out of four to control operation, depending on the mode selected, of various circuits and setting up the content of the registers in the set according to a given meaning.
According to another characteristic, of the four registers two are assigned to define the input/output field address of the MODULO 8 coupler in modes 0, 1, and 3 and MODULO 16 in mode 2.
According to another characteristic, a third register of the four, in the case of mode 0, 1, and 3, defines the size of the extension segment of the basic input/output system, and the read only memory (ROM) segment number of the basic input/output system; and A4 of the address, and one bit for enabling the card;
According to another feature, a fourth register is assigned to define in mode 0:
According to another feature, this fourth register is assigned to define in mode 2:
According to another feature, this same register in mode 1 is assigned to define the size of the random access memory (RAM) window:
This same register is assigned in mode 3 to define a first priority level of the direct memory access (DMA) mode;
According to another characteristic, the arbitration logic, in mode 0 and 3, delivers the bus channel setup request signal LPREEMPT by an arbitration procedure, whereby the ARBGNT signal indicates that an arbitration procedure is under way, the DRQ0 signal indicates a DMA channel request presented by a circuit of the card on the arbitration circuit, the ARB0-3 signals define bus arbitration priority levels, and the DACK0 signal indicates to the card circuit a direct memory access cycle following a request made by the DRQ0 signal.
According to another characteristic, the programmable option selection (POS) register decode circuit, in mode 0 and 3 delivers the LCDEN signals that enable a card on which the circuit is located and the POS register selection signals LCSPOS.
According to another characteristic, in mode 1 and 2 the arbitration logic supplies interrupt level determination signals IT (0-3), memory read command signal LMEMRD, memory write command signal LMEMWR, and random access memory (RAM) selection signal LCSRAM.
The programmable option sel
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"Dynamic Priority Manager Under Application Program Control", A. Couder, et al. vol. 27, No. 4A, Sep. 1984, IBM Technical Disclosure Bulletin, pp. 2216-2218.
"Serial Link Communication Module for Local Work Station Attachments" D. A. Stockwell, vol. 26, No. 6, Nov. 1983, IBM Technical Disclosure Bulletin, pp. 2817-2819.
Auve Glenn A.
Bull S.A.
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