Gating circuit for combining series and parallel connected FETs

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307570, 307585, 307577, H03K 1708, H03K 1712, H03K 1710, H03K 17687

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active

044874570

ABSTRACT:
Gating circuitry is provided for controlling a plurality of power FETs stacked in series and parallel. A plurality of parallel circuit branches are connected between main terminals, each branch having a plurality of series connected power FETs. All power FETs are turned ON and OFF from a single gate terminal. Trigger means responds to one polarity gate signal to supply gate charging current to all the FETs. The trigger means responds to the opposite polarity gate signal to directly deplete gate charge from selected power FETs. The remaining power FETs have their gate charges depleted through individual self turn-off circuits between their gate and source which becomes conductive in the absence of gate charging current.

REFERENCES:
patent: 4277696 (1981-07-01), Tokunaga et al.
Evans, Designing with Field Effect Transistors, McGraw-Hill, Inc., pp. 207-215 and 273-274, 1981.
Kooi et al., "MOS Moves into Higher Power Applications", Electronics, pp. 98-103, Jun. 24, 1976.
Fink et al., Electronics Engineers' Handbook, McGraw-Hill, Inc., pp. 16-15 and 16-16, 1975.

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