Boots – shoes – and leggings
Patent
1993-06-15
1996-04-09
Lall, Parshotam S.
Boots, shoes, and leggings
395440, 364DIG1, 364DIGII, G06F 1300
Patent
active
055069673
ABSTRACT:
In a time-shared bus computer system with processors having cache memories, an adjustable invalidation queue for use in the cache memories. The invalidation queue has adjustable upper and lower limit positions that define when the queue is logically full and logically empty, respectively. The queue is flushed down to the lower limit when the contents of the queue attain the upper limit. During the queue flushing operation, WRITE requests on the bus are RETRYed. The computer maintenance system sets the upper and lower limits at system initialization time to optimize system performance under maximum bus traffic conditions.
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Barajas Saul
Kalish David M.
Whittaker Bruce E.
Axenfeld Robert R.
Kozak Alfred W.
Lall Parshotam S.
Maung Zarni
Starr Mark T.
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