Boots – shoes – and leggings
Patent
1992-04-16
1996-04-09
Lee, Thomas C.
Boots, shoes, and leggings
395301, 3642285, 3642295, 36424292, 36423010, G06F 13368, G06F 1320
Patent
active
055069649
ABSTRACT:
A data processing and transmission network includes plural information processing systems and shared sub-systems remote from the information processing systems. Each shared sub-system includes an I/O bus and a plurality of I/O bus interface logic circuits coupled to the bus. Each interface logic circuit is coupled to one of the system processing devices via a bidirectional fiber optic link, and thereby couples its associated processing device to the I/O bus. Further fiber optic links couple each system processing device to the I/O bus of each remaining sub-system through an associated I/O bus interface logic circuit. Each sub-system further includes multiple I/O devices, each device coupled to a device controller which in turn is coupled to the I/O bus. The bus interface logic circuits and device controllers incorporate arbitration circuitry and communicate with one another via their associated I/O bus, thus to resolve contentions for control of the bus at the sub-system level rather than at the system processor level. These features provide a network with a high degree of redundancy, substantially reduced data access times, and flexibility in network configurations. Regardless of network size, each sub-system I/O device is equally available to all system processing devices, and each system processing device is transparent to the other system processors.
REFERENCES:
patent: 4237534 (1980-12-01), Felix
patent: 4257095 (1981-03-01), Nadir
patent: 4356550 (1982-10-01), Katzman et al.
patent: 4516199 (1985-05-01), Frieder et al.
patent: 4564900 (1986-01-01), Smitt
patent: 4589066 (1986-05-01), Lam et al.
patent: 4607365 (1986-08-01), Greig et al.
patent: 4608631 (1986-08-01), Stiffler et al.
patent: 4608663 (1986-08-01), Gordon
patent: 4701756 (1987-10-01), Burr
patent: 4787033 (1988-11-01), Bomba et al.
patent: 4816990 (1989-03-01), Williams
patent: 4821170 (1989-04-01), Bernick et al.
patent: 4835763 (1989-05-01), Lau
patent: 4837675 (1989-06-01), Bean et al.
patent: 4837856 (1989-06-01), Glista, Jr.
patent: 4964120 (1990-10-01), Mostashari
patent: 5081624 (1992-01-01), Beukema
patent: 5206952 (1993-04-01), Sundet et al.
patent: 5218600 (1993-06-01), Schenkyr et al.
patent: 5301279 (1994-04-01), Riley et al.
patent: 5359715 (1994-10-01), Heil et al.
International Business Machines - Corporation
Lee Thomas C.
Niebuhr Frederick W.
Weinstein Marc K.
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