Patent
1997-11-18
1999-01-26
Lall, Parshotam S.
395389, G06F 930
Patent
active
058646914
ABSTRACT:
First and second circuits store therein source and destination operand addressing information from an instruction code as input information of a main decoder, respectively. A third circuit stores therein information other than operand addressing information from the instruction code as input information of the main decoder. A predecoder analyzes the instruction code and controls states of the first, second and third circuits. A first selector determines which information is input to the main decoder, from the first circuit, the second circuit or the third circuit. A processing selecting circuit causes the first selector to select information for each instruction, in a basic sequence of the first circuit, the second circuit and then the third circuit. The processing selecting circuit controls the first selector so that, if a state of at least one of the first and second circuits indicates that `processing is not required`, the circuit of the state of the indication is not selected and a subsequent circuit is selected instead. The main decoder obtains the information from the first, second and third circuits and controls each component of the central processing unit.
REFERENCES:
patent: H1291 (1994-02-01), Hinton et al.
patent: 5594923 (1997-01-01), Inoue et al.
patent: 5636353 (1997-06-01), Ikenaga et al.
patent: 5651125 (1997-07-01), Witt et al.
Coulter Kenneth R.
Lall Parshotam S.
Ricoh & Company, Ltd.
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