Power static induction transistor fabrication

Details Power static induction transistor fabrication Power static induction transistor fabrication

1981-11-12

1983-03-01

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29580, 148187, 148188, H01L 21225

Patent

active

043751245

ABSTRACT:
A method for fabricating a gate-source structure for a recessed-gate static induction transistor. The method is characterized by use of doped polysilicon to fill the recessed gate grooves after the gate grooves have been etched and diffused. The gate grooves have depth greater than width and therefore the surface of the polysilicon layer deposit is substantially planar. The planar surface allows photolithographic techniques to be used for formation of gate contact regions and for depositing of metal gate and source electrodes.

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Baliga, International Electron Devices Meeting, IEEE, Dec. 1979, pp. 76-78, 784-786.
Nishizawa et al., IEEE Transactions on Electron Devices, vol. Ed-25, No. 3, Mar. 1978, pp. 314-322.
Ohmi, International Electron Devices Meeting, IEEE, Dec. 1979, pp. 84-87.

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