Method of forming a shallow trench isolation region

Details Method of forming a shallow trench isolation region Method of forming a shallow trench isolation region

1997-02-10

1999-11-09

Bowers, Charles

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438437, H01L 2176

Patent

active

059813539

ABSTRACT:
A method of making a shallow trench isolation region which has a reduced kink effect at a subthreshold voltage by forming a shallow trench isolation region, including providing a silicon substrate having a front surface and a backside surface. A first pad oxide layer is c formed over the front surface, and a second pad oxide layer is currently formed over the backside surface. A first silicon nitride layer is formed over the first pad oxide layer, and a second silicon nitride layer is concurrently formed over the second pad oxide layer. The first silicon nitride layer, first pad oxide layer, and the silicon substrate are patterned to form a trench. A side-wall oxide layer is formed within the trench, and a first oxide layer is concurrently formed on a surface of the second silicon nitride layer. A second oxide layer is formed over the first silicon nitride layer and fills the trench. The first oxide layer is removed, and a portion of the second oxide layer is removed. The first silicon nitride layer and the second silicon nitride layer are removed. The removal of the first oxide layer and the subsequent steps are performed in sequence.

REFERENCES:
patent: 4755477 (1988-07-01), Chao
patent: 4876217 (1989-10-01), Zdebel
patent: 5677229 (1997-10-01), Morita et al.
patent: 5712185 (1998-01-01), Tsai et al.
Stanley Wolf Silicon Processing for the VLSI Era vol. 1 pp. 161-164, 1986.

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