Television frame signal synchronizing circuits

Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry

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358149, 375106, H04N 504

Patent

active

045996504

ABSTRACT:
A television frame signal synchronizing circuit comprises a presettable cyclic counter and a maximum count detector, a clock pulse generator for supplying clock pulses to the counter, a store for storing the count of the counter, and a source of reference frame pulses to which input frame pulses are to be synchronized, each reference frame pulse causing the count stored in the store to be loaded into the counter. A television signal processor is capable of adjusting the timing of television signals passed therethrough in dependence on a reverse frame pulse, the carry signals from the counter forming reverse frame pulses for supply to the television signal processor for adjusting the phase of the television signal passed therethrough, the television signal including the input frame pulses at least some of which are derived and supplied to the store which thereupon stores the count of the counter. The phase of the television signal is therefore adjusted until the input frame pulses are in synchronism with the reference frame pulses.

REFERENCES:
patent: 3413414 (1968-11-01), Baldwin et al.
patent: 4203135 (1980-05-01), Sasaki
patent: 4231063 (1980-10-01), Ito et al.

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