Semiconductor memory device having extended period for outputtin

Details Semiconductor memory device having extended period for outputtin Semiconductor memory device having extended period for outputtin

1984-11-23

1987-11-17

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Sequential

365233, G11C 800

Patent

active

047078111

ABSTRACT:
A semiconductor memory device has an operational mode such as a nibble mode or page mode, a first address strobe signal is kept in an active state, and a second address strobe signal is successively switched between an active state and standby state, thereby enabling successive data output. Previous output data is reset once, in accordance with the switchover of the second address strobe signal to the active state while the first address strobe signal is in the active state, before outputting data, and the reset operation for outputting is also performed when both the first and second address strobe signals are switched to the standby state, so that the period in which the data is output is expanded.

REFERENCES:
patent: 4344156 (1982-08-01), Eaton, Jr. et al.
patent: 4376989 (1983-03-01), Takemae
patent: 4602353 (1986-07-01), Wawersig et al.

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