Shifter for shifting floating point number utilizing arithmetic

Details Shifter for shifting floating point number utilizing arithmetic Shifter for shifting floating point number utilizing arithmetic

1995-10-25

1998-03-10

Elmore, Reba I.

Boots, shoes, and leggings

36471508, G06F 700, G06F 738

Patent

active

057269262

ABSTRACT:
Difference between exponents of first and second numbers, based on which an amount of shifting is determined, is represented as a redundant binary number. For groups of bit data pairs of mutually corresponding digits, one shifting means is provided. Each shifting means includes shifting means having fixed amount of bits for shifting corresponding to the amount of shifting represented by the group of input bit data pairs. When a group of bit data pairs is input, one shifting means having fixed amount of bits for shifting of the shifting means is selected, and input number is shifted. By serially connecting the shifting means having such a structure, the first input binary number is successively shifted, and a result shifted by the desired amount is output.

REFERENCES:
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patent: 5526296 (1996-06-01), Nakahara et al.
patent: 5623435 (1997-04-01), Takewa et al.
Fuyuki Okamoto et al, A 200-MFLOPS 100-MHz 64-b BiCMOS Vector-Pipelined Processor (VPP) ULSI, IEEE, Journal of Solid-State Circuits, vol. 26, No. 12, Dec. 1991, pp. 1885-1893.
Hiroshige Fujii et al, A Floating-Point Cell Library and a 100-MFLOPS Image Signal Processor, IEEE, Journal of Solid-State Circuits, vol. 27, No. 7. Jul. 1992, pp. 1080-1088.
Akira Katsuno et al, A 64-bit Floating-Point Processing Unit with a Horizontal Instruction Code for Parallel Operations, IEEE, 1990, pp. 347-350.

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