Frequency synthesizer having jitter compensation

Details Frequency synthesizer having jitter compensation Frequency synthesizer having jitter compensation

1983-10-26

1986-07-08

LaRoche, Eugene

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 18, H03B 700

Patent

active

045995796

ABSTRACT:
A frequency synthesizer includes frequency reduction means which includes a pulse swallow circuit PS which cancels cycles from the frequency Fo under the control of a rate multiplier RM. To prevent phase jitter at the output of phase comparator PC due to the cancelled cycles, a compensation signal HP is derived from a swallow command signal A and from a multiplying fraction n/x of the rate multiplier. In order to keep the DC level of the signal HP constant, the signal HP is bidirectional with respect to a mid-point voltage level and the total area of the pulses in one direction is the same as the total area of the pulses in the other direction. The invention is applicable to both phase locked loop synthesizers (FIG. 2) and direct synthesizers (FIG. 11).

REFERENCES:
patent: 4442412 (1984-04-01), Smith

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