CMOS input level shifting buffer circuit

Details CMOS input level shifting buffer circuit CMOS input level shifting buffer circuit

1986-07-29

1987-11-17

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307469, 307264, 307585, H03K 19092, H03K 1716, H03K 1920

Patent

active

047076232

ABSTRACT:
A binary input signal, V.sub.IN, having a minimum high level value, V.sub.INHMIN, is directly applied to the gate electrode of a pull-up transistor whose conduction path is connected between a first power terminal and an output terminal. V.sub.IN is also applied via level shift circuitry to the gate electrode of a pull-down transistor whose conduction path is connected between the output terminal and a second power terminal. V.sub.IN is level shifted in the positive direction by a preselected voltage level whereby the pull-down transistor is turned-on even when its threshold voltage is approximately equal to V.sub.INHMIN.

REFERENCES:
patent: 4064405 (1977-12-01), Cricchi et al.
patent: 4574273 (1986-03-01), Atsumi et al.

Affiliated with

Also associated with

Rating

CMOS input level shifting buffer circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS input level shifting buffer circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS input level shifting buffer circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1451695